The present invention relates to a phase change memory device and a method for manufacturing the same, and more particularly, to a phase change memory device in which heaters are formed in a self-aligned manner so that the interfaces between the heaters and a phase change layer can be uniformly formed and heat sinks are formed under the heaters so that the amorphous phase of the phase change layer can be stably formed and a method for manufacturing the same.
Generally, memory devices are divided into two categories, i.e., a volatile RAM (random access memory) that loses inputted information when power is interrupted and a non-volatile ROM (read-only memory) that can maintain the stored state of inputted information even when power is interrupted. Examples of the volatile RAM may include a DRAM (dynamic RAM) and an SRAM (static RAM), and an example of the non-volatile ROM may include a flash memory device such as an EEPROM (electrically erasable and programmable ROM) can be mentioned.
Although DRAM is an excellent memory device, the DRAM requires a high charge storing capacity. Therefore, it is difficult to accomplish a high level of DRAM integration since the surface area of an electrode must be increased. Further, in the flash memory device, a high operation voltage is required when compared to a power supply voltage due to the fact that two gates are stacked on each other. Therefore, it is difficult to accomplish a high level of flash memory integration since a separate booster circuit is needed to generate a voltage necessary for write and delete operations.
As a result, research has been actively made to develop a novel memory device having a simple configuration and capable of accomplishing a high level of integration while retaining the characteristics of a non-volatile memory device. For example, a phase change memory device has been disclosed in the art. In the phase change memory device, a phase change occurs in a phase change layer interposed between a bottom electrode and a top electrode from a crystalline state to an amorphous state due to current flow between the bottom electrode and the top electrode. The information stored in a cell of the phase change memory is recognized by the medium of a difference in resistance between the crystalline state and the amorphous state.
One of the most important factors that must be considered in developing a phase change memory device is to reduce programming current. Accordingly, recent phase change memory devices adopt vertical PN diodes as cell switching elements in place of NMOS transistors.
While not shown in a drawing, a phase change memory device employing the vertical PN diodes as cell switching elements includes heaters formed so as to decrease the contact area between the heaters and the phase change layer so that current flow from the cell switching elements can be transmitted to the phase change layer through the heaters.
However, it is difficult to uniformly form the heaters and limitations exist in decreasing the size of the heaters. Therefore, an approach is needed for overcoming these difficulties and limitations.
In addition, when reset programming is implemented in the phase change memory device, i.e., when the phase change layer is quenched after being melted, it is necessary to quickly decrease the temperature of the heaters, because heat transfer occurs to the heaters, so that the phase change layer can stably form an amorphous phase and a reset state with high resistance can be produced.
Although most heat is transferred to the heaters after the phase change layer is melted, nucleation occurs in the melted phase change layer when the phase change layer is not quickly cooled. As a result, a problem is caused in that the nucleation causes a decrease in the reset resistance of the amorphous state. Thus, as the reset resistance of the amorphous phase is decreased, the difference between the reset resistance of the amorphous state and the set resistance of the crystalline state is diminished. Accordingly, the sensing margin of the phase change memory device can be adversely decreased.
In particular, the phase change memory device performs a sensing operation using the difference between the reset resistance of the amorphous state and the set resistance of the crystalline state. Therefore, if the reset resistance is decreased, the sensing margin is correspondingly decreased, whereby the durability of the phase change memory device can deteriorate.